VHDL CODE FOR FULL ADDER
hello friends, after completing the half adder we are taking one step ahead and walking to the FULL ADDER.............
INTRODUCTION
A full adder adds
binary numbers and accounts for values carried in as well as out. A
one-bit full adder adds three one-bit numbers, often written as A,B, and Cin; A and B are the operands, and Cin is a bit carried in from the next less significant stage.[2] The
full-adder is usually a component in a cascade of adders, which add 8,
16, 32, etc. binary numbers. The circuit produces a two-bit output sum
typically represented by the signals Cout and S, where 
. The one-bit full adder's truth table is:
. The one-bit full adder's truth table is:
:)
Keep Visiting
| Inputs | Outputs | |||
|---|---|---|---|---|
| A | B | Cin | Cout | S |
| 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 | 1 |
| 0 | 1 | 0 | 0 | 1 |
| 1 | 1 | 0 | 1 | 0 |
| 0 | 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 1 | 0 |
| 0 | 1 | 1 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 |
and 
.
FULL ADDER can be implemented in 2 ways:-
i)by direct modelling (using basic logic gates).
ii)by using 2 half adders.
HERE I AM POSTING the 2 nd method i.e using 2 half adders.
PROCEDURE
1) Design the half adder . you can use the tutorial i have posted earlier.half adder tutorial
2)Include the half adder as a component in the full adder architecture.
3)Now coding for the full adder using the half adder.JUMP TO THE CODING PART .
4) after coding CHECK THE RTL SCHEMATIC AND THE TECHNOLOGY SCHEMATICS. THEY WILL BE SHOWN PROPERLY.
5)NOW
GENERATE THE TEST BENCH WAVEFORM .WHEN YOU SIMULATE, IT WILL SHOW THE
OUTPUTS UNDEFINED.BECAUSE YOU HAVE NOT TOLD THE LOCATION OF THE HALF
ADDER ON YOUR COMPUTER.
6)
FOR OVERCOMING THIS PROBLEM,IN THE SOURCE BOX,RIGHT CLICK ON THE FILE
WITH DOT VHD EXTENSION AND CLICK ON ADD SOURCE AND THE SOURCE FILE OF
THE HALF ADDER.
7)now again check the test bench waveform . it will be shown properly.
VHDL CODE FOR FULL ADDER USING HALF ADDER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity full_add is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end full_add;
architecture Behavioral of full_add is
component ha is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sha : out STD_LOGIC;
cha : out STD_LOGIC);
end component;
signal s_s,c1,c2: STD_LOGIC ;
begin
HA1:ha port map(a,b,s_s,c1);
HA2:ha port map (s_s,cin,sum,c2);
cout<=c1 or c2 ;
end Behavioral;
NOW JUMP BACK TO THE PROCEDURE.STEP (4).
HOW THE RTL AND TECHNOLOGY SCHEMATIC LOOKS LIKE
NOW LOOKING THE TEST BENCH WAVEFORM
(BEFORE CHECKIN THE TEST BENCH WAVEFORM YOU MUST HAVE PERFORMED THE STEPS 5 AND 6)
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