Half Adder using NAND gate only & Full Adder using NAND gate only

Posted by Unknown Posted on 06:17 with No comments

Half Adder using NAND gate only

fig 3.1

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Full Adder using NAND gate only

To construct a full adder circuit, we’ll need three inputs and two outputs. Since we’ll have both an input carry and an output carry, we’ll designate them as C_IN and C_OUT. At the same time, we’ll use S to designate the final Sum output. The resulting truth table is shown to the right.

Hmmm. This is looking a bit messy. It looks as if C_OUT may be either an AND or an OR function, depending on the value of A, and S is either an XOR or an XNOR, again depending on the value of A. Looking a little more closely, however, we can note that the S output is actually an XOR between the A input and the half-adder SUM output with B and C_IN inputs. Also, the output carry will be true if any two or all three inputs are logic 1.
What this suggests is also intuitively logical: we can use two half-adder circuits. The first will add A and B to produce a partial Sum, while the second will add C_IN to that Sum to produce the final S output. If either half-adder produces a carry, there will be an output carry. Thus, C_OUT will be an OR function of the half-adder Carry outputs. The resulting full adder circuit is shown here ( fig 3.2).,,,,,,,,,,,,,,,,